It is very obvious what we will be doing, and this has been discussed many times: add more metal layers.
Intel processors only have a dozen layers which stack up to less than ~1 um. The numbers of transistors/layers could in theory be increased by 1000x if the layers were stacked ~1 mm high. How to do this with lithographic processes is an open question, but it is absolutely doable in theory. No physical limits prevent us from doing that.
> How to do this with lithographic processes is an open question
You don't, for economic reasons: the latency of chip manufacturing, i.e. time from initial wafer to finished, is already on the order of weeks. Producing more layers lithographically is going to multiply that latency. Not to mention that it would be a nightmare in terms of yield/manufacturing defects.
What is doable (and already done, I believe) is producing multiple chips in parallel and then stacking them on top of each other. Don't think cores spread across multiple layers; think alternating layers of cores and caches, or a layer of cores with layers of memory stacked on top. (This approach doesn't have the yield problem because you can test the chips before you stack them together. It's a technology that is going to see a lot of improvement still.)
Heat transfer is still a problem, though, simply because the number of transistors scales with the volume, i.e. cubically in the "radius", while the surface area available for heat transfer only scales quadratically.
P.S.: When chip people talk about "metal layers", they mean the layers of wiring (also called the BEOL, back-end-of-line). So increasing the number of metal layers does not actually increase the number of transistors. Also, when chip companies talk about "using N layers" in their current technology, that does not mean that N transistors are stacked on top of each other. It means that there is one layer of transistors, and N layers for connecting wires above.
I wonder when we'll start seeing CPUs with integrated heat pumps. Stacking a Peltier junction as a layer could start to make sense. Or even having (non-conductive) fluidic cooling. (Although you have to be careful designing the chip or else capacitive effects can cause problems)
Also, we currently have a heat ceiling on the order of 10s of watts. An integrated liquid-cooled heat sink could drastically up that, at least for server-like applications.
This is not obvious at all. Going 3D makes sense for memory, because these devices aren't heat-limited, but for CPUs it's not at all clear that stacking layers would be a win. CPUs are limited by heat, and heat transport away from the CPU is proportional to area, not volume.
Also, CPU costs are driven mostly by lithography, and if you're doubling the number of high resolution lithography steps, you aren't saving much money compared to just making larger area CPUs.
From a purely seat-of-my-pants-im-trying-to-remember-college point of view, I believe the heat is caused far more by pumping tons of electricity, rather than physical size/layout.
A big problem (and also probably why they're so thin) is that at a certain size latency becomes a huge issue. This is where clock speed increases come into play (electrons move faster) along with die decreases (electrons can travel shorter distances).
If you can run 100mph, but you have to run 200 miles vs. someone who can walk 1mph, but only has to walk 10 feet... I wish I had some more concrete examples but I can't come find anything off the top of my head.
Heat is caused by resistance when the electricity moves through the metal. The more metal the electricity is flowing through, the more material there is incur resistance and generate heat, correct? If so, then more layers = more heat.
> Heat is caused by resistance when the electricity moves through the metal.
Sort of. But if you reduce resistance you increase heat since more current will flow.
On the other hand, if you increase resistance AND also keep the current the same then you'll get more heat. But! to keep that current constant you must increase the voltage.
So it's not so simple as "resistance = heat".
> The more metal the electricity is flowing through, the more material there is incur resistance
Depends on if the metal is in parallel or series. If in parallel, then the more metal the lower the resistance, if in series then higher resistance.
> If so, then more layers = more heat.
Right result, wrong method of getting there. More layers (which would be in parallel) would be less resistance. But less resistance means more current flow (since they'll keep the voltage the same), and more current flow means more heat.
There's also the little matter of defect density. Let's say your 10-layer process yields 50%. Now you go to a 20-layer process, and you should expect your yield to drop to 25%.
(I know, it's not that simple, because there are some defects that are in the underlying substrate. I'm ignoring those for purposes of this discussion.)
What? How does adding metal layers allow you to increase the number of transistors? Transistor density is a fixed function of transistor size, and die size is a variable function ruled mostly by defect density. Unless you are talking about die stacking?
He's referring to 3D density. Die stacking is one way to do that, and it's the only one that isn't just wild fantasy.
Another would be for the die to have multiple layers within a single die - which can't be done with current technology, but isn't physically impossible. Basically what you'd need to do is similar to PCB fabrication - you need to create "blind" and "buried" features within a series of stacked layers.
Obviously that capability doesn't exist right now, but you could look at using an ion beam to create a planar mask that targets only a single layer within a multilayer wafer. The particles travel through material without depositing energy until they reach a critical threshold [1], after which they rapidly deposit nearly all of their energy. This allows you to give the beam a specific "depth", in other words it can be targeted in 3D. Perhaps - because it's a particle beam, not an EM wave - it might also be less susceptible to some of the problems caused by the wave nature of light, even in a more conventional application.
I know it from proton radiotherapy (a good general rundown of the technology here [2]), and I wonder if it couldn't also be used for something like this. A lot of problems would have to be solved. You'd be talking about a substantially different process from standard wafer production, you'd have to tighten up the Z-resolution, etc. No idea if it'd work or not in the end, but I think it'd be interesting to look.
Or alternately maybe we figure out some additive/subtractive method that lets us create multiple layers on a single die another way. For the short terms it's going to be die stacking though.
Unfortunately, particles are also waves. Look at de Broglie waves.
Now, that being said, one real advantage is that the effective wavelength tends to be much smaller. For example, an electron at 0.9c has an effective wavelength of 1.2pm (picometers).
Intel processors only have a dozen layers which stack up to less than ~1 um. The numbers of transistors/layers could in theory be increased by 1000x if the layers were stacked ~1 mm high. How to do this with lithographic processes is an open question, but it is absolutely doable in theory. No physical limits prevent us from doing that.