One of RISC-V's main goals is to be boring and extensible. Think if it as the control-plane core, or the EFI for a larger system. You would take RISC-V and use it drive your novel VLIW processor.
How? RISC-V will have to have memory model, for example, which will define some at least effective execution model. If you turn RISC-V into not RISC-V you might as well just start from scratch.
Nah I think the Itanic concept is dead in the water
VLIW works (especially in the way it was done in Itanium - IIRC) when either your workload is too predictable or maybe if your compiler manages to be one order of magnitude smarter than it is today (even with llvm, etc)
It seems even M1 prefers to reorder scalar operations than work with SIMD ops in some cases (this is one of its processors)
AMD and Nvidia both used VLIW in the past and both moved away because they couldn't get it to run efficiently. If embarrassingly parallel problems can't execute efficiently on VLIW architectures, I somehow doubt that CPUs will either.
The final versions of Itanic started adopting all the branch predictors and trappings from more traditional chips.
The problem is that loops theoretically cannot be completely predicted at compile time (the halting problem). Modern OoO CPUs are basically hardware JITs that change execution paths and patterns on the fly based on previous behavior. This (at least at present) seems to get much better data resulting in much better real-world performance compared to what the compiler sees.
It's a shame the Mill is so secretive, actually, they're design is rather nice.