It doesn't really bother me as we've seen it coming for years. Anyone playing smart is not relying on a process node jump rather than better architected systems. I think the fact that they bought Altera and might do on-board FPGA logic more than balances out here. I'll take an FPGA-accelerator on their on-chip NOC over an incremental increase in performance/energy any day. Even big companies such as Microsoft are wisening up to the fact that a proper split between CPU and FPGA logic has significant advantages.
I'm curious to see what AMD will do in response to both the delays and Altera acquisition. Wait, a quick Google shows AMD to be so bad off that a FPGA company (Xilinx) might buy them. Lol. Ok, well the market is about to get interesting again one way or the other.
It could get interesting. Of course, for secure CPU developers, FPGA's have been the solution for stopping malware rather than the problem. Too bad we only have prototypes to work with so far. Remember, though, that there's always anti-fuse (write-once) FPGA's available for a design you don't plan to change.
Those are overhyped so as to be buzzwords. All the IO-MMU really does is make the data come to and go from a certain point of memory. What it does when it hits the system software or applications is a whole, different risk area. See OS process separation vs all the ways it's bypassed with app & kernel-level vulnerabilities.
So, you consider that the FPGA might sabotage data you send through it or what comes from it. Be monitoring or doing validation on both.
There's plenty of low watt FPGA's, even mW's. The Cyclones, etc get 4,000+MIPS in under 2 watts. Microsemi already does FPGA's that run milliwatts with enough slices to support 5-6 accelerators concurrently. As the example below shows, you can have two Stratix's, a CPU, and a whole board's worth of stuff using only 45watts. Merely adding a few layers to an SOC at Intel's new nodes should use way less power than all that. I'm sure Altera's, with Intel's help, will be pretty sweet given they're mainly targeting datacenter use where performance-per-watt is key criteria.
Still, worst case, I'll gladly add 45watts to a gaming/workstation rig... which probably already has a several hundred watt power supply... in exchange for Stratix IV's 500,000+ LE's, 20Mbit SRAM, 20+ 8.4Gbps transceivers, and more direct CPU-to-FPGA link. You have no idea what I can do with that amount of logic and interface speed. A whole OpenSPARC T1 setup only takes 173,000 LE's. Most extensions to make highly secure processors take up a small fraction of that.
So many possibilities and so little time/money. :)
I wonder how many people forget (or never learned) that unlike the X86, MIPS, ALPHA, and ARM architectures, SPARC is an open standard and anyone can make a 100% ISA compatible SPARC CPU...
SPARC deserves much more love from the open hardware community than I see it receiving.
Upvote for you seeing as you're educated on the subject! :) I've been telling these secure CPU teams to use it for a while. A few have but most didn't. SAFE went with discontinued, but still I.P., Alpha. (rolls eyes) Shit, the Oracle SPARC T1 & T2 processors were first real CPU's to go open source! Here was my recommendation for open hardware crowd in another HN thread:
"The RISC-V activity is very interesting. I particularly love that they did a 1.4GHz core on 48nm SOI and are working on 28nm level. This knocks out some of the early, hard work of getting competitive hardware at an advanced process node. I'd like to see two things in this work: microprogrammed variant with an assembly or HLL to microcode compiler; tagged variant like SAFE/CHERI processors with IO/MMU that seemlessly adds & removes tags during DMA. That would be way better for security-critical applications than most of what's out there. Multi-core would help, too.
Meanwhile, Gaisler's SPARC cores are commercial, open-source, customizable, support up to 4 cores in Leon4, integrated with most necessary I.P., and can leverage the SPARC ecosystem. Anyone trying to do an open processor can get quite the head-start with that. A few academic and commercial works are already using it. Plus, the SPARC architecture is open as such that you only pay around $100 for the right to use its name.
So, Gaisler's SPARC cores with eASIC's Nextreme seems to be the best way to rapidly get something going. The long-term bet is RISC-V and they could do well copying Gaisler's easy customization strategy. Might be doing that already with their CPU generator, etc: I just read the Rocket paper so far. The solutions built with one can include a way to transition to the other over time."
The Cyclone IV "MIPS" you are talking about comes from the built-in ARM cores so you're comparing ASIC to ASIC here.
An FPGA vs ASIC, FPGA will lose every time. It is a simple matter of architecture. You have more crap to make the FPGA an FPGA, whereas in ASIC you have optimized gates. So it doesn't make sense for Intel to ship FPGA + CPU for consumer/mobile. Period. You burn more power and no one needs it. FPGAs are also more expensive because they take a ton of silicon space for a comparable function.
FPGA SoCs like Xilinx Zynq or Altera's offerings are widely used but for specific applications, none of it really consumer/mobile/desktop.
Stratix IV FPGAs that you are talking about are many thousands of dollars, each. You can get them today and hang them off your PCIe bus and do whatever you want with them. There is nothing stopping you. Putting it on the same die as a CPU won't buy you anything you don't get today -- except a lot of more heat you have to get rid of.
I don't think electrical engineering works the way you think it does.
For reference: I've designed ASICs and have done a lot of FPGA work in the past 10 years.
In lay terms, an FPGA is a chip that rewrites itself to be customized for a given use (or uses). Can rewrite themselves as many times as needed and very fast, too. Flexibility means more price, more watts, and less performance than truly custom chip. Yet, having custom circuits for the job can make an application SCREAM with performance. Here's some concepts for you.
1. Compression, encryption, etc that's many times faster (50x on some algorithms).
2. Do high-end streaming workloads (eg HD video, NIDS) on embedded hardware with hardly any watts.
3. Put specialized audio, AI, whatever engines in the FPGA for video games that take it to the next level with a whole CPU left for main game logic.
4. Implement a concurrent, hardware, garbage collector to write your whole OS in memory-safe language and not have freezes due to GC.
5. Use onboard I/O, often many lanes at Gbps, to get crazy throughput on any number of disk, networking, wireless, etc use-cases.
6. Use custom I/O for real-time applications.
7. Simulate other forms of hardware on the FPGA for personal learning or product development. Can deploy it in production on FPGA boards later.
8. Forget software emulators: build the hardware itself on the FPGA and have accurate simulation.
9. Cutting edge techniques do something similar with mockups of normal hardware which are modified to spot the exact time and place certain bugs happen. Then you can see everything from the input that caused it to the internal state of the processor. And fix it.
10. My use-case: processors modified to prevent code injection or data leaks to run applications that hackers can't hit. Altera's I'd use for prototyping then put them on anti-fuse FPGA's: write-once FPGA's that blow circuits intentionally to prevent attackers or glitches from modifying the system's logic. ROP that, bitches!
In short, you can use FPGA's for anything you can use a custom circuit for. They'll just be a bit weaker and usually depend on a host system to set them up. Common case is to have main CPU do most of the work with FPGA's accelerating it or handling interfaces (I/O) in a way they're better at. I'd say Google on FPGA hobby projects, use cases, "applications," etc to see the $3+ billion worth of uses for them. In case you're not drooling, here's a startup that's currently the top performer:
That joker has over a Gigahertz speed, 6 DDR3 lanes, up to 64 lanes of 12.75Gbps serial I/O, up to 16 of 28Gbps serial I/O, up to 400Gbps Ethernet, 400Gbps Interlaken (datacenter thing), and 2 PCI/Express controllers. Add 1.7 million LUTS for custom logic w/ 138 Mbits of registers or cache... noting that one of those mighty Oracle SPARC T1 processors only needs about 400,000 LUTS... to get a beast of a machine. Those are $10,000 unsurprisingly. Yet, even units that are several hundred dollars can do a hell of a lot and Altera on Intel's process node will do more.
I agree with another commenter that we'll see them in servers and datacenters first. The reason is that they'll have to charge more to recoup the initial cost of making them. Chips aint cheap: probably $5-10+ million per silicon test on Intel's node with mistakes requiring you to spend again. Tools to reduce that start at $1+ million a seat. Good thing FPGA's don't cost all that and have free/cheap synthesis tools. ;)
Sold. So what are the chances that we get PC architecture like this someday? Do you think it may sneak in the backdoor through graphics card manufacturers? Games seem like a huge application.
Previously, they went through the PCI bus (FPGA cards), custom memory bus (SGI's Altix), or PC memory bus (Pico Mini). The statements I've been reading on Intel's acquisition of Altera indicate they might integrate them at the SOC level. That knocks out most of what latency exists over the memory buses. The resulting performance for apps split between the CPU and FPGA should be much higher if they do this.
" through graphics card manufacturers? "
They actually compete with graphics card manufacturers with different tradeoffs. Most likely, your system will have a graphics card and FPGA logic.
"So what are the chances that we get PC architecture like this someday?"
I have no idea how much it costs. You could probably buy a powerful server cheaper given it has four, good FPGA's (unit prices always high). Yet, that's a Core i7, up to 32GB of RAM, and 6 FPGA's worth of custom logic connected to both. Mainly aimed at FPGA developers and the niche that use them for acceleration. I'm sure hobbyists with cash might enjoy it, too. :)
I'll end with an illustration. A company once made a dedicated physics chip (Physx) to dramatically improve game physics while CPU did other things. NVIDIA acquired it & added it to GPU. Latest demo (below) on ever-difficult water rendering shows what a custom chip can do for an element of gaming. Now, just list off in your head all the other things that make a game work and imagine what it might be like if they had custom circuits too. And each game had its own custom circuits. Probably like PS3 vs PSX in difference. Not sure if it will happen, but we can keep dreaming, right?
They'll certainly progress. Far as IBM's announcement, they said they could do it in a lab but not mass manufacturing. Intel says they can't mass manufacture things yet. So, the two could be in a similar situation where they have lab-proven concepts but nothing further. Too little data for me to know at this point.
I'm curious to see what AMD will do in response to both the delays and Altera acquisition. Wait, a quick Google shows AMD to be so bad off that a FPGA company (Xilinx) might buy them. Lol. Ok, well the market is about to get interesting again one way or the other.