Wow, you are so wrong, and yet no one has corrected you!
We want to increase gate capacitance, not decrease it.
The higher the capacitance, the faster you can invert the channel, and therefore turn the transistor on.
Think of a transistor as a water tap (valve based). Gate capacitance is the sensitivity of the valve to the handle. In this analogy, higher capacitance is equivalent to less effort to turn the handle (to move the valve out of the way and let the water flow).
That's the reason we want to increase the area of the gate (the idea behind FinFET, and all-around gate), and increase its dielectric constant (the idea behind high-k materials).
You're also confused about RC model - perhaps you heard it in the context of a logic gate (as in NAND), and you try to apply it when talking about a transistor gate (as in FinFET). Nope.
We want to increase gate capacitance, not decrease it. The higher the capacitance, the faster you can invert the channel, and therefore turn the transistor on.
Think of a transistor as a water tap (valve based). Gate capacitance is the sensitivity of the valve to the handle. In this analogy, higher capacitance is equivalent to less effort to turn the handle (to move the valve out of the way and let the water flow).
That's the reason we want to increase the area of the gate (the idea behind FinFET, and all-around gate), and increase its dielectric constant (the idea behind high-k materials).
You're also confused about RC model - perhaps you heard it in the context of a logic gate (as in NAND), and you try to apply it when talking about a transistor gate (as in FinFET). Nope.