SRAM takes up a tremendous amount of space compared to logic. Usually at least six transistors per bit, plus passives, plus management logic.

SRAM is big in gate count. typically 6 transistors per bit.

The i386, a 32 bit chip already dragging around a couple of generations of legacy architecture came in at 275,000. I would imagine the Hazard3 would be quite a bit more efficient in transistor usage due to architecture.

16K is 16384(bytes) *8(bits per byte) *6(transistors per bit) = 786, 432

It was the first CPU on my desk! 80386SX 25MHz.

(this one, only 32bit internally)

Thanks for the explanations - was not aware.

…vertically stack a slab of SRAM above or beneath the CPU die, does come to mind ;)

This is way too expensive for something like a microcontroller. AMD calls this 3D V-Cache and uses it on their top end SKUs.

But doesn't the ESP32-S3-WROOM have some large on-chip RAM?

For the Pico, say, something in the line of the approach taken by many smartphone SoCs that package memory and processor together.

The ESP32-S3 has 512 KB of SRAM, and the RP2350 has 520 KB of SRAM. The ESP32-S3-WROOM does indeed come in configurations with additional PSRAM, but that would be comparing apples and pears. The WROOM is an entire module complete with program flash, PSRAM, crystal oscillator etc. It comes in a much larger footprint than the actual ESP32-S3, and it is entirely conceivable that one could create a similar module with the same amount of PSRAM using the RP2350.

Furthermore, the added RAM in both cases is indeed PSRAM. That being said, the ESP32-S3 supports octal PSRAM, not just quad PSRAM, which does make a difference for the throughput.

> "some"

And go cellphone style: Package-on-Package or Multi-Chip Module of some sort.

Wouldn't the massive increase in capabilities from adding 8MB-16MB of closely-integrated, fast RAM far outweigh the modest price increase for many applications that are currently memory-constrained on the Pico?

> But doesn't the ESP32-S3-WROOM have some large on-chip RAM?

They use the same PSRAM chips with relatively bad latency you complained about higher up in the thread. There are boards like those from Pimoroni that even have them on the PCB from the factory.

> For the Pico, say, something in the line of the approach taken by many smartphone SoCs that package memory and processor together.

What for? This only saves you PCB space, the latency is not going to be affected by this. There probably won't be enough people ordering those to justify the additional inventory overhead of (at least) 2 more skews.

I believe there's already a separate Flash die in the same package. Probably not possible to add yet another die for DRAM.

(for various chemistry reasons, it's much more efficient to manufacture Flash, DRAM, and regular logic on separate wafers with different processing)