Indeed that's how nearly all NAND flash works nowadays, early SLC media was binary with each cell set to a low or high voltage, but as density increased they started using more voltages inbetween to encode multiple bits per cell. The current densest NAND uses 16 different positive voltage states to encode 4 bits per cell.
Most "SLC" and "MLC" that's sold is actually TLC/QLC hardware that's only using a subset of the voltage levels available. It ends up being significantly cheaper due to the economies of scale in manufacturing.
Yep, if you ever come accross the term "pSLC" (Pseudo-SLC) that means the underlying hardware is capable of running in MLC/TLC/QLC mode, but the controller firmware has been configured to only use the lowest and highest voltage state in each cell.
Some SSD controllers will also reassign regions of flash to different modes on the fly, the drives unused capacity can be used internally as a very fast pSLC write cache, and then as the drive fills up those cells incrementally get switched over to the native TLC/QLC mode.
Very interesting. I would have thought the overhead from the memory controller would negate all savings, but I know very little about modern cell design.
If you want to do it in a single step, you need 8 analogic comparators at the output of the memory, and one level of "and" and "or" gates to solve each bit.
Most ADCs use a single comparator + OpAmp and convert the value in 3 steps. But that would make your memory slower.
Either way, the task of converting it does not fall over the controller.
