Would you be willing to back and try to optimize this for pure output speed?

I thought the exact same question, but wondered if FPGA's gate connections are too distant for FizzBuzz to beat 55 GiB/s.

With an FPGA, the speed limit will 100% be how you want to output the data.

If you require it to come out of IO pins, then the limit will be the total output bandwidth of all the serdes units on the IO pins. Typically that's much more than 55GiB/s.

Just had a quick look at the cheap FPGA dev boards and on my basic search the clock speeds seems to be in the low 1-10GHz range.

But this task could be scaled up with parallel FPGA boards in sync

It isn't clock speed that matters, but the number of IO pins and the rate the serdes units can be clocked.

Eg. Stratix V GX devices offer up to 66 integrated transceivers with 14.1-Gbps data rate.

Thats ~1Tbps right away from a single $500 device.

When I saw this I did wonder how much faster I could do it in hardware, but similarly I expect the bottleneck would be outputting it in a fashion that would be considered fair to be compared to software implementations (eg outputting readable text on a screen).

Regardless, I very much enjoyed your DVD screensaver-esque output.

At that point we are writing firmware for the display

GPU memory is an order of magnitude higher bandwidth than RAM, so that would seem to me to be the way to go to beat this. The output wouldn’t be accessible from CPU without a big slowdown though.

Ah, but the M1Max is unified memory, isn't it?

And am I doing the math right that a quintillion fizzbuzz will take about 7 months?

I would be doubtful since most FPGAs have a much lower clock speed than CPUs. Maybe unless you take advantage of parallelism.