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> And this is why they will fail. RISC-V suffers hugely from NIHS and would have no chance against any competition in a real market without that artificial hype. They need to get better.

I'm sorry but that is nonsense. An ISA (unless its a utterly terrible one) simply is not what determains performance.

RISC-V will be useful for performance because you can make a good cores far easier then if you used any other ISA. RISC-V is well optimized for performance and future standard extensions will give the micro-architect a lot of options to make performant chips.

Furthermore, why do they suffer from NIHS? The whole ISA is quite literally designed to be a relatively conservative design that specifically build on the knowledge gained by others in the last 30 years. Its the exact opposite of NIHS. The only NIHS is that you are complaining about is that they did something new at all.

> The fully GPL licensed OpenSPARC T2 is more advanced than anything RISC-V has to offer even though it is ten years old. Why reinvent the wheel when you can build on top of existing solutions that has proven itself on millions of machines including two top 100 Computer clusters.

SPARC is now owned by Oracle and only SPARC V8 is an open standard. The OpenSPARC T2 is v9. Do you really think its good to start a new revolutionary compute project on something so strongly tied to Oracle?

You are aware that some of the same people who helped design SPARC also designed RISC-V. You can listen to their explanations of why they didn't want SPARC, specially not for a what is designed to be a universal ISA.

> This is also true for SPARC.

No its not. SPARC is not a modular ISA in the same way RISC-V is and the RISC-V believe that a modular ISA will be needed.



Why are you spreading so much misinformation?

> only SPARC V8 is an open standard. The OpenSPARC T2 is v9.

"Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL." - Wikipedia

> No its not. SPARC is not a modular ISA in the same way RISC-V is and the RISC-V believe that a modular ISA will be needed.

"The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set" - Wikipedia


The RTL can be open without the ISA being open.

> "The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set" - Wikipedia

Yes. SPARC is a RISC and therefore it can scale well in implementation. RISC-V however has taken the modular approach to ISA design far further then anything else has so far.

Again, maybe you should actually read about the design of RISC-V and why the didn't want to adopt SPARC.

You accuse me of spreading misinformation, but you don't seem to know what the difference between SPARC and RISC-V are.




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