> seamlessly handle any alignment with perhaps an extra cycle I'm not up to date... | Hacker News

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		jjoonathan on Nov 7, 2016 \| parent \| context \| favorite \| on: A bug story: data alignment on x86 > seamlessly handle any alignment with perhaps an extra cycle I'm not up to date on the latest mitigation strategies, but the hairball of cache implications caused by unaligned access make me suspicious of that claim. If you (or your compiler) signal that you want performance by using vector instructions, I think it's completely fair for Intel to demand that you pay attention to alignment.

qb45 on Nov 8, 2016 [–]

Case in point: a simple example of code which copies 1MB of data with SSE and slows down on misalignment:

https://news.ycombinator.com/item?id=12718625

Presumably due to the hairball of cache implications, as you put it.

But it also is true that the choice of aligned/unaligned instructions makes no difference if the array is aligned.

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