That's a pretty good indication that there is a big problem. Deep at the heart of it is that processor designers don't quite understand the performance characteristics of their processors any more, so they cannot produce e.g. an abstract memory model that compiler writers could base their optimisations on.
Optimisations for parallel processing, e.g. auto-parallelisation are not well developed either.
Oh, I think Intel knows it, but they consider it too much of a trade secret to even tell the compiler team about it.
There are actually numerous performance counters exposed by the CPU too, which are good for dynamic benchmarking, but hardly anyone cares to use them.
BTW, even though the ALU part of the CPU is extremely wide and dynamic, you still have to fit your instructions through the x86 decoder at the front, and it's worth writing a scheduler just to model that part.
I understand that they need to keep the low level details
of their CPU secret, but a memory model? All it says is when/how reads and write commute. If a CPU manufacturer were to
provide a nice, high-level memory model, this would make the CPU more sellable. Why? Because compiler writers could more aggressively optimise when compiling for the CPU.
I suspect that the reason they don't give out memory models is that
they don't know how to do it. That's also the vibe I've been getting
when I talked to people who would know.
Optimisations for parallel processing, e.g. auto-parallelisation are not well developed either.