It is likely the hardware effiency of their chips. Apple SoCs running industry-standard benchmarks still run very cool, yet still show dominant performance. The OS efficiency helps, but even under extreme stress tests like SPEC, the Apple SoCs dominate in perf & power.
> It is likely the hardware effiency of their chips. Apple SoCs running industry-standard benchmarks still run very cool, yet still show dominant performance
1) Apple Silicon outperforms all laptop CPUs in the same power envelope on 1T on industry-standard tests: it's not predominantly due to "optimizing their software stack". SPECint, SPECfp, Geekbench, Cinebench, etc. all show major improvements.
2) x86 also heavily relies on micro-ops to greatly improve performance. This is not a "penalty" in any sense.
3) x86 is now six-wide, eight-wide, or nine-wide (with asterisks) for decode width on all major Intel & AMD cores. The myth of x86 being stuck on four-wide has been long disproven.
4) Large buffers, L1, L2, L3, caches, etc. are not exclusive to any CPU microarchitecture. Anyone can increase them—the question is, how much does your core benefit from larger cache features?
5) Ryzen AI Max 300 (Strix Halo) gets nowhere near Apple on 1T perf / W and still loses on 1T perf. Strix Halo uses slower CPUs versus the beastly 9950X below:
1. Apple’s optimizations are one point in their favor. XNU is good, and Apple’s memory management is excellent.
2. X86 micro-ops vs ARM decode are not equivalent. X86’s variable length instructions make the whole process far more complicated than it is on something like ARM. This is a penalty due to legacy design.
3. The OP was talking about M1. AFAIK, M4 is now 10-wide, and most x86 is 6-wide (Ryzen 5 does some weird stuff). X86 was 4-wide at the time of M1’s introduction.
4. M1 has over 600 reorder buffer registers… it’s significantly larger than competitors.
> 4. M1 has over 600 reorder buffer registers… it’s significantly larger than competitors.
And? Are you saying neither Intel nor AMD engineers were able to determine that this was a bottleneck worth chasing? The point was, anybody could add more cache, rename, reorder or whatever buffers they wanted to... it's not Apple secret-sauce.
If all the competition knew they were leaving all this performance/efficiency on the table despite there being a relatively simple fix, that's on them. They got overtaken by a competitor with a better offering.
If all the competition didn't realize they were leaving all this performance/efficiency on the table despite there being a relatively simple fix, that's also on them. They got overtaken by a competitor with better offering AND more effective engineers.
>> x86 is now six-wide, eight-wide, or nine-wide (with asterisks) for decode width on all major Intel & AMD cores. The myth of x86 being stuck on four-wide has been long disproven.
From the AMD side it was 4 wide until Zen 5. And now it's still 4 wide, but there is a separate 4-wide decoder for each thread. The micro-op cache can deliver a lot of pre-decoded instructions so the issue width is (I dunno) wider but the decode width is still 4.
A whole lot of bluster in this thread but finally someone whose actually doing their research chimes in. Thank you for giving me a place to start in understanding why this is so deeply a mystery!
2. uops are a cope that costs. That uop cache and cache controller uses tons of power. ARM designs with 32-bit support had a uop cache, but they cut it when going to 64-bit only designs (look at ARM a715 vs a710) which dramatically reduced frontend size and power consumption.
3. The claim was never "stuck on 4-wide", but that going wider would incur significant penalties which is the case. AMD uses two 4-wide encoders and pays a big penalty in complexity trying to keep them coherent and occupied. Intel went 6-wide for Golden Cove which is infamous for being the largest and most power-hungry x86 design in a couple decades. This seems to prove the 4-wide people right.
4. This is only partially true. The ISA impacts which designs make sense which then impacts cache size. uop cache can affect L1 I-cache size. Page size and cache line size also affect L1 cache sizes. Target clockspeeds and cache latency also affect which cache sizes are viable.
Thus, it will be more than 15,000 employees for sure. :(
//
Written another way: at least 1 in 7 Intel employees will be let go. I don't know how a CPU & foundry can fire 15% in two quarters without significant negative repercussions.
I would've preferred the gov't handing Intel a check and expecting, in return,
1) ownership stake of Intel, including governance, for xx years
2) stock buyback ban
3) stock dividend ban
4) golden parachute ban
5) far more public disclosures of progress, setbacks, and other problems
If Intel—who's spent BILLIONS on buybacks—can't find enough money from the debt or equity or private markets, then, yes, serious strings should be required.
Currently, CHIPS only receives some profit sharing and that's it.
There were way too many alternative ways to implement this and we're paying the price of picking a "winner" that is massively cocky and arrogant with abysmal results. Major mistake and unlikely to deliver because it got wads of cash with very few serious strings attached.
Just exposed yesterday:
>The company is permanently grounding the Intel Air Shuttle, which flies workers between its major sites in Hillsboro, Silicon Valley and Arizona.
>The company stopped the flights last year then resumed flying in April. The shuttle was especially prized by Oregon employees, who sought to avoid the 30-mile drive across the metro area to Portland International Airport.
>The decision to permanently ground the shuttle, just five months after reinstating it, suggests that Intel executives didn’t recognize the severity of their financial situation until very recently.
That’s well and good for Intel, why would TSMC agree to any of those terms? You’re forgetting that CHIPS wasn’t just hand outs for Intel, but to bring other fabs to the US.
Projected to be better by Intel and Intel alone. Intel has disclosed virtually no details of Intel 18A on any industry-standard metric: perf / W with an Arm core, transistor density; precise perf & density improvements over Intel 4, 3, and 20A.
TSMC is far, far more transparent than Intel—which is backwards. Intel is who needs more customers. Intel's silence on 18A's specifics is not inspiring.
Qualcomm resoundingly rejected Intel 18A, according to the Wall Street Journal, due to Intel missing multiple promised 18A milestones.
>Qualcomm, which designs chips and outsources manufacturing, wanted to work with Intel, and assigned a team of engineers to work toward making mobile-phone chips at Intel’s factories. It was particularly interested in a cutting-edge chip-making technology that Intel hopes will be the most advanced in the world by late next year.
>In early 2022, Intel’s foundry arm sent a delegation to Qualcomm’s San Diego headquarters, where they met with CEO Cristiano Amon. Then Intel missed a June performance milestone toward producing those chips commercially. It missed another in December.
>Qualcomm executives concluded Intel would struggle making the kind of cellphone chips they wanted, even if it succeeded in making high-performance processors. Qualcomm told Intel it was pausing work while it waits for Intel to show progress, according to people involved in the discussions.
Without Qualcomm, Intel has only found one real customer after a half-decade of hype: UMC's design subsidiary Faraday is an "evaluation [sever] platform" with Arm Neoverse cores, while Microsoft is making a vague "custom" chip.
Faraday won't even sell those CPUs (it's an ASIC firm primarily) and Microsoft couldn't be bothered to give a single word of detail of what they are producing.
I'm not hopeful, yet, until someone actually ships a key product on Intel 18A.
This is purely a DIY problem for six-month old systems.
Not a single OEM desktop or laptop sold in the past six months as new should have any of these issues.
UEFI is non-negotiable, TPM 2.0 is virtually universal, and you only need to be Secure Boot capable—not actually have Secure Boot on.
This tool expects the person that built the computer (Dell, HP, Lenovo, or the DIY enthusiast) to understand the terms.
But, credit to the author, it presents them in a very poor way. It should’ve noted UEFI / GPT wasn’t enabled first before any other error. But it assumes you know UEFI requires GPT which means using mbr2gpt.exe.
Thank you so much for starting this project and hopefully long-term investment. Incredibly refreshing.
The site is down for the moment. What is the situation about warranty?
Do you plan to offer multi-year options? I’m all for repairing my own laptop, but if there is an option to pay upfront for some peace of mind on at least the parts, I’d bite.
Thank you for the reply. Great to hear it's on Framework's radar.
While the reparability helps (as I'm used to even $800 laptops calling for $300 screens + webcam + Wi-Fi antenna), if it's profitable for Framework, it'd be an instant buy here.
Agreed. Zen3 would’ve been killer and cooler to boot.
I wonder if it is a supply concern? Zen2 laptops also ~seemed~ in scarce supply for quite some time last year, even after the launch.
How to tease out Intel’s anti-competitive belligerence versus actual supply issues? Zen3 on desktop seems to be regularly available, but desktop is lower volume than mobile.
This really deserves an AMD variant.
I would suspect Intel has juicy bundle discounts, especially if this is a part of the EVO program (which I don’t think it publicly is).
I think it’s down again if you click the configurations. Home page is sometimes up, but that’s also down some of the time.
“ 500 Internal Server Error
If you are the administrator of this website, then please read this web application's log file and/or the web server's log file to find out what went wrong.”
See Lunar Lake on TSMC N3B, 4+4, on-package DRAM versus the M3 on TSMC N3B, 4+4, on-package DRAM: https://youtu.be/ymoiWv9BF7Q?t=531
The 258V (TSMC N3B) has a worse perf / W 1T curve than the Apple M1 (TSMC N5).